Trivial FPGA/LUT Demo

Reset 0 K Clock 1 Power MUX/DEMUX A A Quad 1-input LUT 0 Always 0 1 Invert 0 Passthrough 1 Always 1

Development status: Designed, drawn, and refactored.
"Parked" in a valid live configuration.
Next, Making switchable, adding javascript, adding live-logic.

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